`include "define.v"
module select_PC
    (
	input  [31:0] M_valA,
	input  [31:0] W_valM,
	input  [31:0] predPC,
	input  [7:0] M_opcode,
	input  [7:0] W_opcode,
	input  [2:0] f_stat,
	input  M_cnd,
	output reg  [31:0] f_pc
    );


    always @ (M_opcode,W_opcode,M_valA,W_valM,predPC,M_cnd,f_stat)
    begin
      if(f_stat==`ST_HLT)
			 if(M_opcode[7:4]=={`NORM_INS,`GROUP_JMP} && ~M_cnd)
				f_pc<=M_valA;
			 else
				f_pc<=f_pc;
		else
		begin
			if(M_opcode[7:4]=={`NORM_INS,`GROUP_JMP} && ~M_cnd)
				 f_pc<=M_valA;
			else if(W_opcode=={`NORM_INS,`RET})
				 f_pc<=W_valM;
			else if(M_opcode=={`NORM_INS,`HALT})
				 f_pc<=f_pc;
			else
				 f_pc<=predPC;
		end
    end


endmodule


